Allwinner /D1H /UART[1] /HALT

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as HALT

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disabled)halt_tx 0 (disable)chcfg_at_busy 0 (finished)change_update 0 (not_invert)sir_tx_invert 0 (not_invert)sir_rx_invert 0 (dma_pte_rx)dma_pte_rx 0 (pte)pte

sir_rx_invert=not_invert, change_update=finished, chcfg_at_busy=disable, sir_tx_invert=not_invert, halt_tx=disabled

Description

UART Halt TX Register

Fields

halt_tx

0 (disabled): undefined

1 (enabled): undefined

chcfg_at_busy

0 (disable): undefined

1 (enable): undefined

change_update

0 (finished): undefined

1 (update_trigger): undefined

sir_tx_invert

SIR TX Pulse Polarity Invert

0 (not_invert): undefined

1 (invert): undefined

sir_rx_invert

SIR RX Pulse Polarity Invert

0 (not_invert): undefined

1 (invert): undefined

dma_pte_rx

The Transmission of RX_DRQ

pte

The sending of TX_REQ

Links

()